High Performance Microcontrollers and Interfaces

• Computer architectures (1 lecture)

• Definitions (instruction set, micro- and computer architecture), dynamic and static interface, characteristics of a good architecture, motivation of development, stages of development, virtual machines, relations among levels, compilation and interpretation, computer generations.

• Microarchitectures (2 lectures)

• Performance of processors: Iron law, simple-, super- and superscalar pipeline processors, VLIW processors, Amdahl’s law.
• Organization of simple pipeline processors (principle, Earle puffer, highest frequency), arithmetic pipeline, fix point and floating-point arithmetic, instruction pipelines, typical 6-phase pipeline, implementation, real pipelines (RAW, WAW, WAR and control hazards and eliminating them).
• Superscalar organization: parallel pipelines, diversified pipelined and dynamic pipelines, hazards and their elimination, register renaming, branch prediction.
• P6 microarchitecture: 3 independent motor, elements of microarchitecture and their functions.

• Graphics processors (2 lectures)

• Resolution, color depth, speed, functionality, 2D and 3D graphics in GPUs, graphics pipeline, general purpose applications of GPUs.

• ARM Cortex A processor family (3 lectures)

• Features of ARM Cortex A processor family
• Digital signal processing features in modern controllers: requirements, example of a FIR filter, typical signal processing architectures, circular buffers, MAC, fast loop handling, hardware stack, special addressing modes.

• Multiprocessor systems (1 lecture)

• Methods increasing speed, classification of multiprocessor systems, control flow, data flow, demand driven, pattern drives systems. Multicore processors vs. multiprocessor system.
• Representative systems: systems with local and global memory, solving temperature distribution of a plane. Tightly and loosely coupled MIMD systems.
• Cache coherency: write back and write through systems, software and hardware methods, directory based and snooping protocols.

• General characteristics of interfaces and buses (1 lecture)

• Mechanical characteristics
• Electrical characteristics
• Logical characteristics.

• SATA bus (1 lecture)

• General features, layer structure, physical layer (mechanical and electrical features), data link layer (sending and receiving frames, scrambling, 8b/10b encoding, primitives), transport layer (FIS editing, communication with the data link layer, FIFO puffer management, etc.).
• SATA Express bus.

• USB bus (2 lectures)

• General characteristics: system architecture (bus topology, devices and endpoints), system configuration, connection and disconnection, dataflow types, speed and bandwidth allocation, layer structure of hardware and software.
• Mechanical interface features: A and B type connectors, mini USB connector, On-The-Go specification, cables.
• Electrical features: drivers and receivers, signal levels, J and K states, HUB and devices, speed identification, encoding.
• Logical features: elements of data transmission, packets in a transaction (token, data and handshaking packets), IN, OUT, SETUP and special packets, transactions, USB descriptors, configuration.
• USB 3.0 features.

• PCI bus system (1 ½ lectures)

• Need of its introduction, family members.
• PCI Express bus: advantages of serial technology, system architecture, layer structure. Element of the physical layer (multiplexers, byte stripping logic, scramblers, 8b/10b encoders, parallel-to-serial converters, clock derivation, word alignment, signal de-emphasis). Packet based  layer protocol (data link layer and transaction layer packets, quality of service, virtual channels and traffic classes).

• Thunderbolt interface ( ½ lecture)

• General features of SoC (1 lecture)

• SoB, SoC, PSoC and SoP systems, advantages, disadvantages.
• IP reuse: soft, hard and firm IP blocks, analog and mixed signal blocks.
• Communication infrastructure: socket and AXI based infrastructures.

• Soft processors (1 lecture)

• Elements of Spartan 6 family: clock network, configurable logic blocks, IO blocks, memory elements, DSP slice.
• PicoBlaze architecture and resources.
• MicroBlaze architecture, register structure, instruction set, optional elements, memory interfaces, IP elements, MicroBlaze MCS.

• Zynq: FPGA based PSoC (2 lectures)

• Architecture: ARM Cortex-A9 processor (PS), programmable logic (PL), AXI interfaces between PS and PL.
• PS elements: Application Processing Unit (APU), memory interfaces, IO peripherals (IOP), Central interconnect.