Circuit Design from Abstraction to Realisation

After discussing the characteristics of the abstraction levels and optimization goals of complex digital system design, the different formal language means of high level programming techniques such as procedural and object-oriented paradigms are presented by instruction set simulator examples. The Register-Transfer Level (RTL) modeling is the central topic of the second part of the semester. This part of the course also demonstrates the SystemC-based HW/SW co-design paradigm and the methods applied in cycle-accurate modeling using SystemC, furthermore, the techniques used in synthesizable VHDL modeling is discussed as well by presenting the synthesizable VHDL implementations of the exemplary instruction set simulators. The course provides an overview of the implementation techniques of complex digital circuits, namely the standard cell ASIC, CPLD and FPGA technologies. In the last part of the semester the modern functional verification methodologies are discussed, such as e language and eRM verification.

Week 1.: Abstraction levels in the digital system modeling
Week 2.: Algorithmic modeling of microprocessors: procedural approach
Week 3.: Algorithmic modeling of microprocessors: object-oriented approach
Week 4.: Overview of VHDL: synthesizable language constructs for RTL modeling
Week 5.: VHDL-based RTL design
Week 6.: RTL optimization I.: basics
Week 7.: RTL optimization II.: Clock Domain Crossing (CDC), Reset
Week 8.: RTL optimization III.: datapath optimization: resource requirement, timing, power-consumption
Week 9.: RTL modeling of microprocessors
Week 10.: Overview of SystemC, creating cycle-accurate models from procedural algorithmic models using SystemC wrappers
Week 11.: Implementation technologies: stdcell ASICs, CPLDs, FPGAs
Week 12.: ASIC verification I.: basics
Week 13.: ASIC verification II.: eRM verification methodology
Week 14.: Mid-semester check