Rendszerszintű tervezés laboratórium

A tantárgyleírás hatályossága

Hatályosság kezdete:

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Hatályosság vége:

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Subject name (Hungarian, English)

Rendszerszintű tervezés laboratórium

Subject code

BMEVIEEMSFB003-00

Subject type

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Training Level

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Course types and hours (weekly/semester)

Course type	lecture	tutorial	laboratory
hours (weekly)	0	0	4
type (linked/independent)	—	—	autonomous course

Assessment type

félévközi érdemjegy

Credits

Subject coordinator

Khafajy Osama Ali Salman

contact: osama.khafajy@vik.bme.hu

Responsible department

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Faculty

Subject website

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Primary curriculum type

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Direct prerequisites – Strong prerequisite

none

Direct prerequisites – Weak prerequisite

none

Direct prerequisites – Parallel prerequisite

none

Direct prerequisites – Milestone prerequisite

none

Direct prerequisites – Exclusion

none

Objectives

Programme

Detailed syllabus of tutorials/labs

1. VHDL Language Structure and basic coding examples.

2. Hierarchical Design Using VHDL and component instantiation practice.

3. Operators and Attributes: Practical examples and simulations.

4. Sequential logic in VHDL (Part 1)

5. Sequential logic in VHDL (Part 2)

6. Implementing sequential logic and State Machines.

7. Design Implementation Using Quartus II (Part 1)

8. Design Implementation Using Quartus II (Part 2)

9. Frequency Measurement Circuit Design (Part 1)

10. Frequency Measurement Circuit Design (Part 2)

11. Introduction to Twin Builder and VHDL-AMS workflows

12. Analog and Mixed-Signal Design practice using VHDL-AMS

13. Advanced Twin Builder simulations and mixed-signal environments

14. System-Level Design: Hardware and Software co-simulation using SystemC

The objective of the "System Level Design Laboratory" is to provide hands-on, practical experience with industry-standard Electronic Design Automation (EDA) tools. Students will apply the theoretical knowledge gained in the System Level Design lectures to real-world engineering problems. Through a series of guided laboratory sessions, students will write, simulate, and synthesize VHDL and SystemC code. They will gain practical proficiency in hierarchical design, mixed-signal simulation using Twin Builder, and FPGA implementation using tools like Quartus II.

Learning outcomes

Ez a tantárgy a KKK rendeletben meghatározott, következő kompetenciák fejlesztését szolgálja:

Knowledge

No learning outcomes recorded.

Skills

No learning outcomes recorded.

Attitudes

No learning outcomes recorded.

Autonomy and responsibility

No learning outcomes recorded.

Oktatási módszertan

4 hours of computer laboratory sessions per week.

Tanulástámogató anyagok

Online források

• Electronic lab manuals and guides provided by the department (available on the Faculty Moodle platform).; • Official EDA tool documentation (e.g., Quartus II, Twin Builder).; • Peter J. Ashenden, "The Designer's Guide to VHDL".

Recommended preliminary knowledge for completing the subject

Knowledge type competencies

(azon előzetes ismeretek összessége, amelyek megléte nem kötelező, de a tantárgy eredményes teljesítését nagyban elősegíti)

Digital logic basics, VHDL fundamentals

Skill type competencies

(azon előzetes képességek és készségek összessége, amelyek megléte nem kötelező, de a tantárgy eredményes teljesítését nagyban elősegíti)

nincs

Recommended (non-compulsory) preliminary competencies

(azon ajánlott (nem kötelező) előzetesen megszerzendő kompetenciák összessége, amelyek jelentősen hozzájárulnak a tantárgy eredményes teljesítéséhez)

Digital logic basics, VHDL fundamentals

General rules

Requirements: During the semester Successful completion of the laboratory sessions and timely submission of lab reports • During the semester, one out of the prescribed number of laboratory exercises can be missed and one additional failed session can be re-taken. • Preparedness is checked at the beginning of each lab; unprepared students may be dismissed. • The final grade (midterm mark) is determined by the quality of the submitted lab reports and practical in-lab performance Additional possibilities: During the semester, one missed or failed laboratory session can be re-taken. Foreign language requirements: N/A

Assessment methods

In-term assessments

No detailed assessments provided.

Weight of in-term assessments

No weights provided.

Exam-period assessments

No detailed assessments provided.

Weight of exam elements

No weights provided.

Grade calculation

No grade thresholds provided.

Attendance requirements

No attendance requirements provided.

Rules for retake and resubmission

Not provided.

Short description

Not provided.

Detailed description

IMSc program: N/A IMSc points: N/A

Recommended courses

Prerequisites: System Level Design is recommended.

Workload to complete the subject

No workload breakdown provided.

Validity of subject requirements

Requirements valid from:

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Requirements valid until:

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Curriculum placement

No curriculum placements recorded for this subject version.