Subject » BMEVIHIAA02
Computer Architectures
Számítógép-architektúrák
A tantárgyleírás hatályossága
Hatályosság kezdete:
2026. March 21.
Hatályosság vége:
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| Subject name (Hungarian, English) |
Számítógép-architektúrák
Computer Architectures
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| Subject code | BMEVIHIAA02 | ||||||||||||
| Subject type | — | ||||||||||||
| Training Level | — | ||||||||||||
| Course types and hours (weekly/semester) |
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| Assessment type | vizsga | ||||||||||||
| Credits | 4 | ||||||||||||
| Subject coordinator |
DR. Horváth Gábor
position: egyetemi tanár
contact:
horvath.gabor@vik.bme.hu
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| Responsible department |
Hálózati Rendszerek és Szolgáltatások Tanszék
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| Faculty | Villamosmérnöki és Informatikai Kar | ||||||||||||
| Subject website | — | ||||||||||||
| Primary curriculum type | — | ||||||||||||
| Direct prerequisites – Strong prerequisite | none | ||||||||||||
| Direct prerequisites – Weak prerequisite | none | ||||||||||||
| Direct prerequisites – Parallel prerequisite | none | ||||||||||||
| Direct prerequisites – Milestone prerequisite | none | ||||||||||||
| Direct prerequisites – Exclusion | none |
Objectives
Programme
Introductory topics. Information processing models. Control driven architectures: Neumann, Harvard and modified Harvard architectures.
I/O devices. Dedicated I/O instructions vs memory mapped communication. Flow control. Processing the signals of the peripherals: polling, interrupt, interrupt in multi-processor environment, interrupt moderation. Decreasing the load of the CPU: DMA, I/O processor. I/O peripheral interconnects: busses, point-to-point connections, serial vs. parallel lines, timing, arbitrations. Systems with a single bus, multiple busses, south- and north bridge. PCI, PCI Express and USB peripheral interfaces.
Mass storage drives. The main operation of hard disk drives: sectors, zoned bit recording. Components of the delay of read and write requests. Command queueing. The physical operation of SSDs. Aging, data unit of operations, the unique implementation of the write requests. The tasks of the SSD controller: garbage collection, wear leveling, data compression, over-provisioning.
Memory systems. Synchronous DRAM based system memory: the role of the memory controller, memory modules, ranks, and banks. The DRAM commands and their timing, out-of-order scheduling of the commands. Virtual memory: address translation, TLB, page table implementations, single-level and multi-level page tables. Address space separation. Cache memory: the locality of references, cache organization, relation with the virtual memory. Cache content management: pollution avoidance, pre-fetch, block replacement algorithms. Locality aware programming techniques.
Processor. Instruction set architectures, CISC and RISC strategies. Pipeline instruction processing. The hazards and their resolutions. The implementation details of a simple 5-stage instruction pipeline. Introducing multiple functional units with non-equal delay. Dynamic instruction scheduling (out-of-order execution). The precedence graph and the data-flow execution of the instructions. The role of the instruction window, register renaming and re-order buffer. The Tomasulo algorithm. Wide pipelines: superscalar, VLIW and EPIC architectures. Branch prediction: predicting the outcome and the target address of branches. Branch prediction aware programming.
Parallel processing. Data parallelism: vector processors, SIMD instructions, array processors. Multiprocessor systems: the notion of explicit parallelism, multi-threaded processors. Classification of multiprocessor systems. Cache coherence and memory consistency problems in shared memory multiprocessor systems.
For the practices:
- Reviewing the digital design knowledge through a simple hardware-software design problem
- I/O devices: CPU load computations with polling and interrupt-based I/O
- Mass storage drives: HDD response time and throughput computations, SSD write management algorithms
- Memory systems: DRAM command scheduling, delay computations, virtual memory exercises with and without TLB
- Cache memory: Examples for cache organizations. Cache miss ration computations for small C programs, optimization.
- Pipeline scheduling: Instruction scheduling for low level programs for particular pipelines, optimal instruction scheduling
- Advanced pipeline techniques: Dependency analysis, eliminating anti-dependencies with register renaming. Optimizing for branch prediction in small C programs.
The objective of the course is to provide deep knowledge to the students on the internals, operation and properties of computers. Getting familiar with the characteristics of the hardware allows to develop efficient software that utilizes the computer’s resources as much as possible.
Learning outcomes
Ez a tantárgy a KKK rendeletben meghatározott, következő kompetenciák fejlesztését szolgálja:
Knowledge
No learning outcomes recorded.
Skills
No learning outcomes recorded.
Attitudes
No learning outcomes recorded.
Autonomy and responsibility
No learning outcomes recorded.
Oktatási módszertan
Lectures: one lecture every week
Classroom practices: one practice every second week
Tanulástámogató anyagok
Online források
Lecture slidesDavid A. Patterson, John L. Hennessy. Computer Organization and Design, Morgan Kaufmann Publishers, 2011.Jean-Loup Baer. Microprocessor Architecture, Cambridge University Press, 2010.Bruce Jacob, Spencer W. Ng, Samuel Rodriguez. Memory Systems, Morgan Kaufmann Publishers, 2008.William Stallings. Computer Organization and Architecture, 2012.
Recommended preliminary knowledge for completing the subject
Knowledge type competencies
(azon előzetes ismeretek összessége, amelyek megléte nem kötelező, de a tantárgy eredményes teljesítését nagyban elősegíti)
nincs
Skill type competencies
(azon előzetes képességek és készségek összessége, amelyek megléte nem kötelező, de a tantárgy eredményes teljesítését nagyban elősegíti)
nincs
Recommended (non-compulsory) preliminary competencies
(azon ajánlott (nem kötelező) előzetesen megszerzendő kompetenciák összessége, amelyek jelentősen hozzájárulnak a tantárgy eredményes teljesítéséhez)
nincs
General rules
Requirements:
There is one mid-term test during the semester, it has to be successfully accomplished in order to get the signature.
To get the credit, a successful exam is required in the exam period.
Additional possibilities:
It is possible to re-take the mid-term test in the last week of the semester and in the re-take week.
Assessment methods
In-term assessments
No detailed assessments provided.
Weight of in-term assessments
No weights provided.
Exam-period assessments
No detailed assessments provided.
Weight of exam elements
No weights provided.
Grade calculation
No grade thresholds provided.
Attendance requirements
No attendance requirements provided.
Rules for retake and resubmission
Not provided.
Short description
Not provided.
Detailed description
Not provided.
Recommended courses
Not provided.
Workload to complete the subject
No workload breakdown provided.
Validity of subject requirements
Requirements valid from:
—
Requirements valid until:
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Curriculum placement
No curriculum placements recorded for this subject version.