Microelectronics Design
A tantárgyleírás hatályossága
| Subject name (Hungarian, English) |
Mikroelektronikai tervezés
Microelectronics Design
|
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| Subject code | BMEVIEEAC01 | ||||||||||||
| Subject type | — | ||||||||||||
| Training Level | — | ||||||||||||
| Course types and hours (weekly/semester) |
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| Assessment type | vizsga | ||||||||||||
| Credits | 4 | ||||||||||||
| Subject coordinator |
Horváth Péter
position: adjunktus
contact:
horvath.peter.2@vik.bme.hu
|
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| Responsible department |
Elektronikus Eszközök Tanszéke
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| Faculty | Villamosmérnöki és Informatikai Kar | ||||||||||||
| Subject website | — | ||||||||||||
| Primary curriculum type | — | ||||||||||||
| Direct prerequisites – Strong prerequisite | none | ||||||||||||
| Direct prerequisites – Weak prerequisite | none | ||||||||||||
| Direct prerequisites – Parallel prerequisite | none | ||||||||||||
| Direct prerequisites – Milestone prerequisite | none | ||||||||||||
| Direct prerequisites – Exclusion | none |
Objectives
1.
Implementation of digital circuits (full-custom,
semi-custom, PLA, CPLD, FPGA, etc.). Implementation alternatives of different
hardware devices,
2.
Cooperative design and manufacture from full-custom to
FPGA. The tasks of the designer,
3.
Hardware-software co-design,
4.
Design flow, production flow,
5.
Synchronous and asynchronous digital circuits. General
issues of low power design,
6.
Virtual Component (VC) and intellectual property (IP)
based design,
7.
Static and dynamic CMOS and BiCMOS circuit
implementations,
8.
Circuit simulation, models, model parameters,
9.
Logic simulation, definition of models and parameters
from circuit simulation,
10. Functional and
structural tests,
11. Failure-models,
structural test generation, failure simulation. Digital test automation. Design
for testability, scan-path,
12. Design systems (CAD,
Mentor, Cadence), top-down, bottom-up design style.
13. Masks and technologies
necessary for integrated circuit manufacture. Layout design rules,
14. Cell placement and
routing algorithms,
15. Design with HDL. Steps
of synthesis. Verilog commands and their effect on synthesis. Synthesis and
timing. Timing analysis, wire-load model, preliminary placement,
16. Structure and
operation of microprocessors, microcontrollers and signal processors. Neumann
and Harvard processors. Static and dynamic memories.
17. Technology-dependent
design steps of FPGA devices (format converters, logic partitioning, placement
and routing modules),
18. Structure, operation,
dissipation and costs of GPP, FPGA, SoC, SiP, microcontroller devices,
19. Program and data
memory. I/O operations, interrupt, DMA handling, adaption and operation of input
devices and displays in programmable devices,
20. Simulation, testing, calibration,
cost-efficiency.
The course has a laboratory practice (2 hours/week)
1.
Introduction of the design of a complete ASIC
specification as a use-case. The role of the designer as the contact person
between the procurer and the manufacturer should be highlighted,
2.
Use-case of a digital system design. E.g. washing
machine controller ASIC described in Verilog using top-down methodology and
hierarchy,
3.
Design for testability. Introduction of ad-hoc methods
on concrete circuits. Extension of an ASIC with scan-path circuit, demonstrated
with simulations.
4.
Usage of programmable devices in circuit realization,
5.
Demonstration of alternatives after circuit synthesis
(ASIC vs. FPGA),
6. Demonstration of the synthesis of a moderately complex ASIC Verilog description.
7. Demonstration of floorplanning from description to full chip layout.
Learning outcomes
Ez a tantárgy a KKK rendeletben meghatározott, következő kompetenciák fejlesztését szolgálja:
Knowledge
No learning outcomes recorded.
Skills
No learning outcomes recorded.
Attitudes
No learning outcomes recorded.
Autonomy and responsibility
No learning outcomes recorded.
Oktatási módszertan
Tanulástámogató anyagok
Online források
Recommended preliminary knowledge for completing the subject
General rules
Assessment methods
In-term assessments
No detailed assessments provided.
Weight of in-term assessments
No weights provided.
Exam-period assessments
No detailed assessments provided.
Weight of exam elements
No weights provided.
Grade calculation
No grade thresholds provided.
Attendance requirements
No attendance requirements provided.
Rules for retake and resubmission
Not provided.
Short description
Not provided.
Detailed description
Not provided.
Recommended courses
Workload to complete the subject
No workload breakdown provided.
Validity of subject requirements
Curriculum placement
No curriculum placements recorded for this subject version.